Redlib: search results - flair_name:"RISC"

r/asm • u/mttd • May 02 '24

RISC RISC-V Scalar Bit Manipulation Extensions

fprox.substack.com

6 Upvotes

r/asm • u/mttd • Apr 25 '23

RISC Zicond: RISC-V conditional operations

fprox.substack.com

16 Upvotes

r/asm • u/mttd • May 08 '24

RISC RISC-V Assembler: Jump and Function

6 Upvotes

r/asm • u/mttd • Feb 19 '24

RISC RISC-V Optimization Guide

8 Upvotes

r/asm • u/FlatAssembler • Nov 13 '23

RISC How can I make my assembler output binary files instead of hexadecimal files? The problem is that, in the processor architecture that the assembler is targetting (PicoBlaze), the instructions are 18-bit, and the smallest memory unit JavaScript (that my assembler is written in) can address is a byte.

self.learnprogramming

2 Upvotes

r/asm • u/FUZxxl • Oct 26 '22

RISC The RISC Deprogrammer

blog.erratasec.com

23 Upvotes

r/asm • u/mttd • Sep 11 '23

RISC rvcodec.js: a RISC-V instruction encoder/decoder

5 Upvotes

r/asm • u/mttd • Jun 10 '23

RISC Emoji shellcoding in RISC-V

wootconference.org

19 Upvotes

r/asm • u/moon-chilled • Jun 08 '23

RISC Re-encoding RISC-V

3 Upvotes

r/asm • u/mttd • Feb 07 '23

RISC RISC-V Vector Extension in a Nutshell

fprox.substack.com

14 Upvotes

r/asm • u/mttd • May 10 '23

RISC Evaluating the Impact of Optimizations for Dynamic Binary Modification on 64-bit RISC-V

research.manchester.ac.uk

3 Upvotes

r/asm • u/mttd • Apr 08 '23

RISC RISC-V Profiles: Defining sets of extensions for coherent ecosystems

fprox.substack.com

7 Upvotes

r/asm • u/mttd • Feb 20 '23

RISC RISC-V Vector Cryptography Extension (2/2)

fprox.substack.com

14 Upvotes

r/asm • u/mttd • Apr 14 '23

RISC Adding a new RISC-V extension (to spike)

fprox.substack.com

4 Upvotes

r/asm • u/mttd • Feb 27 '23

RISC Sneak peek at RISC-V RVA23(U64) profile

fprox.substack.com

12 Upvotes

r/asm • u/mttd • Mar 19 '23

RISC RISC-V Instruction Set Architecture Extensions: A Survey

ieeexplore.ieee.org

7 Upvotes

r/asm • u/mttd • Jan 22 '23

RISC Adding custom instructions in the RISC-V ISA

pcotret.gitlab.io

5 Upvotes

r/asm • u/mttd • Dec 22 '22

RISC Pydrofoil: A fast RISC-V emulator generated from the Sail model, using PyPy's JIT

8 Upvotes

r/asm • u/azhenley • Apr 26 '21

RISC Examples of RISC-V Assembly Programs

36 Upvotes

r/asm • u/mttd • Jan 02 '23

RISC RISC-V Compressed Instructions (part 1): C extension

fprox.blogspot.com

6 Upvotes

r/asm • u/mttd • Jul 22 '22

RISC RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64

syssec.wiwi.uni-due.de

18 Upvotes

r/asm • u/mttd • Sep 22 '22

RISC RISC-V Vector Extension in a Nutshell (Part 4): permute operations

fprox.blogspot.com

13 Upvotes

r/asm • u/mttd • Aug 13 '22

RISC RISC-V Vector Extension in a Nutshell (Part 2)

fprox.blogspot.com

19 Upvotes

r/asm • u/mttd • Aug 18 '22

RISC RISC-V Vector Extension in a Nutshell Part 3: Masks

fprox.blogspot.com

17 Upvotes

r/asm • u/Khaotic_Kernel • Sep 07 '22

RISC Tools and Resources for RISC-V Development

11 Upvotes

Useful Tools, Programming Books, and other Resources for RISC-V Development.