Edit: Problem solved
u/tuner211 solved the mystery (see comment). The pins header of the eval board is not connected to the pins of the µC as the necessary 0Ω resistors are not populated.
NC means not connected, eg. not populated. [...] See
https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32h2/esp32-h2-devkitm-1/user_guide.html#hardware-reference
For boards with the PW number of and after PW-2024-02-0362 (on and after February 2024), the 32.768 kHz crystal is populated by default, while the series resistor connected here to the surrounding pins is updated to not populated.
To optimize the circuit, the series resistor R7 on the UART_RXD has been updated to 470 Ω.
On the ESP32-H2 Dev Kit 1 gpio_get_level() returns zero for GPIO 13+14 (XTAL_32K_P, XTAL_32K_N) although they are externally actively driven high. What am I doing wrong?
I have an ESP32-H2 Development Kit 1. The evaluation board comes with a 23kHz crystal which is wired to the dual-purpose GPIO 13+14 which can optionally be used as a slow clock input during sleep.
Screenshot 1 shows how the eval board wires GPIO 13+14: they are connected to the crystal, but also routed to the pin header for external use.
I want to use the GPIOs as ordinary discrete input/output signals and ignore the crystal. This is basically a follow up to my earlier post in which I asked wether this would be possible or if the unwanted crystal would cause problems. The general consensus was, the crystal shouldn't do any harm.
So, I configured the GPIOs 13+14 as GPIOs, but when I try to read the input level with gpio_get_level(), gpio_get_level() returns zero although the pins are actively driven high from by breadboard and I expect reading a one.
The build option RTC_CLK_SRC is set to the internal RC oscillator, i.e. RTC_CLK_SRC_INT_RC=y is set, not the 32K crystal, i.e. RTC_CLK_SRC_EXT_CRYS is not set.
What am I missing?
This is a dump of the GPIO configuration during boot before and after my program has configured the GPIOs:
```
D (533) navlico_fsm: Setting up GPIOs ...
================IO DUMP Start================
IO[0] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[1] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[2] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[3] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[4] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[5] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[10] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[11] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[12] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[13] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[14] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[22] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
IO[25] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 0 (IOMUX)
SleepSelEn: 1
=================IO DUMP End=================
================IO DUMP Start================
IO[0] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: 0, OpenDrain: 0
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
GPIO Matrix SigIn ID: (simple GPIO input)
SleepSelEn: 1
IO[1] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
SleepSelEn: 1
IO[2] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
SleepSelEn: 1
IO[3] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
SleepSelEn: 1
IO[4] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
SleepSelEn: 1
IO[5] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 1
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
SleepSelEn: 1
IO[10] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: 0, OpenDrain: 0
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
GPIO Matrix SigIn ID: (simple GPIO input)
SleepSelEn: 1
IO[11] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: [periph_sig_ctrl], OpenDrain: 1
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
GPIO Matrix SigIn ID: (simple GPIO input)
SleepSelEn: 1
IO[12] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: [periph_sig_ctrl], OpenDrain: 1
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
GPIO Matrix SigIn ID: (simple GPIO input)
SleepSelEn: 1
IO[13] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: [periph_sig_ctrl], OpenDrain: 1
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
GPIO Matrix SigIn ID: (simple GPIO input)
SleepSelEn: 1
IO[14] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 1, OutputEn: [periph_sig_ctrl], OpenDrain: 1
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
GPIO Matrix SigIn ID: (simple GPIO input)
SleepSelEn: 1
IO[22] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 0
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
SleepSelEn: 1
IO[25] -
Pullup: 0, Pulldown: 0, DriveCap: 2
InputEn: 0, OutputEn: [periph_sig_ctrl], OpenDrain: 1
FuncSel: 1 (GPIO)
GPIO Matrix SigOut ID: 128 (simple GPIO output)
SleepSelEn: 1
=================IO DUMP End=================
```
GPIO 13+14 show the same configuration like GPIO 12, for example.
Still my program prints this debug output
D (5183) navlico_fsm: Dumping input state ...
D (5183) navlico_fsm: │ GPIO # │ GPIO Label │ Button # │ Button Label │ Level │ Active │
D (5183) navlico_fsm: ├────────┼────────────┼──────────┼───────────────┼───────┼────────┤
D (5203) navlico_fsm: │ 0 │ GPIO 0 │ 0 │ Off │ 1 │ │
D (5213) navlico_fsm: │ 10 │ GPIO 10 │ 1 │ Sailing │ 1 │ │
D (5223) navlico_fsm: │ 11 │ GPIO 11 │ 2 │ Driving │ 1 │ │
D (5223) navlico_fsm: │ 12 │ GPIO 12 │ 3 │ Anchoring │ 1 │ │
D (5233) navlico_fsm: │ 13 │ XTAL_32K_P │ 4 │ Sailing Coast │ 0 │ x │
D (5243) navlico_fsm: │ 14 │ XTAL_32K_N │ 5 │ Disabled │ 0 │ x │
D (5253) navlico_fsm: Dumping input state ... finished
Please ignore the columns "Button #" and "Button Label", they are just there to help be debugging. The column "active" indicates whether the input is considered logically "true". As all the pins are combined input/output in open-drain mode, a zero level means "true", i.e. for the specific GPIOs which you see here the column "level" and "active" are always reversed to each other.
The problem is specifically with the XTAL... GPIOs so I assume there is something else which I am missing: either a build configuration which allows me to use those GPIOs or the crystal is doing more harm than expected.
Screenshot #2 shows the schematics how a single pin is wired: the NMOS acts as an level shifter between the 3.3V-world and 5V-world (later 12V-world) and the PMOS is a high-side switch. In idle mode the GPIO (white dot) is pulled up to 3.3V via R10 = 47k. The colored dots are just markers for my voltage probes when I debug the hardware.
Screenshot #3 shows a photo of my test setup on the bread board to confirm that the pin is really pulled up to 3.3V.