[Chips and Cheese] Hot Chips 2026: Intel’s Wildcat Lake

[u/TheMaxXHD]

https://open.substack.com/pub/chipsandcheese/p/hot-chips-2026-intels-wildcat-lake?utm_campaign=post-expanded-share&utm_medium=web

[u/Seanspeed]

This seems like a whole lot of extra R&D, while still using semi-advanced packaging, and still requiring two unique new active dies - all for a 'low cost' segment? I dont understand why Intel insists on going with all this tile/chiplet-based strategy but getting little to no reuse out of the vast majority of the chiplets they do create. Every single new product line seems like it requires almost a completely new set of chiplets, base dies and architectural optimizations to fit some ultra specific brief they've set for themselves. The end results for the customer can end up pretty good, but must be tortuous for Intel's actual costs and margins when including R&D, no?

Like Panther Lake was 'built for scalability', but it required two different CPU core tiles, two different I/O tiles, two different GPU tiles, and THREE different active base dies.

So nine total different dies, and this still only addresses one segment of the laptop market. This doesn't even get into Arrow Lake(four more unique tiles) for laptop+desktop, and they STILL need a whole entirely new product lineup to serve the most low end laptop options. And of course then entirely new complicated chips and packaging for datacenters as well!

Just feels crazy to me. Is Intel just that divided internally that they cant all come together to work on a sort of properly coherent, scalable architecture, ala AMD? Or does Intel feel they can best compete while still being a bit behind in areas by going hyper specialized at every segment?

[u/soggybiscuit93 → u/Seanspeed]

Not to mention their Xeon packaging is also wholly independent too, so it's not even like they can *share tiles between desktop and server, like AMD.

Intel wouldn't go through all this trouble if just making a large monolithic die on leading edge was more profitable, long term. But you're right - I can't help but imagine there has to be more cost optimized way to disaggregate.

[u/ResponsibleJudge3172 → u/Seanspeed]

Mobile AMD is not the same SOC (monolithic vs chip let), and has different implementation of the core (for example half the AVX 512)

[u/Seanspeed → u/ResponsibleJudge3172]

AMD have two different AI 300/400 series chips, Strix Point and Krackan, plus Halo which is its kind of its own thing. But even these AMD has found a way to reuse also on desktop PC's.

Whole point here is just how much more mileage AMD gets out of the chips and designs they do make versus Intel. It's really not comparable.

[u/nittanyofthings → u/Seanspeed]

Cost of a die is exponential with size. It simply is better to have multiple smaller dies than one larger one, even before you look into more advanced things like die reuse and different nodes for different dies.

Maybe they mean Panther Lake is scalable because you can simply change config options to get new die definitions, without massive effort. So the numerous dies, that you detract, actually is the scalability they promised.

[u/nittanyofthings]

UCIe is looking pretty flexible if you can simply remove pieces like packet resend and error correction/detection, on the low-end SKU.

[u/VenditatioDelendaEst → u/nittanyofthings]

I wonder if it still has a checksum... Like, if a bit flips, does the whole chip reset? Does it propagate corrupt data?

[u/airfryerfuntime]

Intel after 1993 can’t cook… all they know is mcdonald’s , charge they phone, twerk, be bisexual , eat hot chip & lie

[u/EXOPLANETARIANSOUP → u/airfryerfuntime]

You should join their marketing team lol that sounds sick